Francesco Centurelli

Author Info

Name	Affiliation	Papers
FRANCESCO CENTURELLI	Univ Roma La Sapienza, Dipartimento Ingn Elettron, Via Eudossiana 18, I-00184 Rome, Italy	37
Collaborators	Citations	PageRank
50	56	15.93
Referers	Referees	References
122	375	136

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100375

Publications (37 rows)

Collaborators (50 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers	0	0.34	2022
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic	0	0.34	2021
A Low-Voltage High-Performance Frequency Divider Exploiting Folded Mcml	0	0.34	2021
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops	0	0.34	2021
Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications	0	0.34	2021
Delay models and design guidelines for MCML gates with resistor or PMOS load	0	0.34	2020
0.6-V Cmos Cascode Ota With Complementary Gate-Driven Gain-Boosting And Forward Body Bias	1	0.37	2020
Low-Power Class-Ab 4(Th)-Order Low-Pass Filter Based On Current Conveyors With Dynamic Mismatch Compensation Of Biasing Errors	0	0.34	2020
An Improved Reversed Miller Compensation Technique For Three-Stage Cmos Otas With Double Pole-Zero Cancellation And Almost Single-Pole Frequency Response	0	0.34	2020
A low-power class-AB Gm-C biquad stage in CMOS 40nm technology	0	0.34	2019
High-Gain, High-Cmrr Class Ab Operational Transconductance Amplifier Based On The Flipped Voltage Follower	0	0.34	2019
A Topology of Fully-Differential Class-AB Symmetrical OTA with Improved CMRR	0	0.34	2018
A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR.	0	0.34	2018
Fully Differential Class-AB OTA with Improved CMRR.	0	0.34	2017
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption	5	0.57	2016
A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier	0	0.34	2016
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks	5	0.45	2015
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer	0	0.34	2014
A wideband amplifier topology based on positive capacitive feedback	1	0.41	2014
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters	8	0.79	2013
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters.	5	0.58	2012
A very low-voltage differential amplifier for opamp design.	1	0.37	2011
A class-AB flipped voltage follower output stage.	5	0.70	2011
A class-AB very low voltage amplifier and sample & hold circuit.	0	0.34	2011
An MDAC architecture with low sensitivity to finite opamp gain.	0	0.34	2011
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies	13	0.92	2009
A simple technique for fast digital background calibration of A/D converters	1	0.36	2008
CMOS High-CMRR Current Output Stages	4	0.86	2007
A statistical model of logic gates for Monte Carlo simulation including on-chip variations	1	0.38	2007
A Distortion Model For Pipeline Analog-To-Digital Converters	1	0.38	2007
Validation Of A Statistical Non-Linear Model Of Gaashemt Mmic'S By Hypothesis Testing And Principal Components Analysis	0	0.34	2006
A model for the distortion due to switch on-resistance in sample-and-hold circuits	2	0.72	2006
A 10-gb/s CMU/CDR chip-set in sige BiCMOS commercial technology with multistandard capability	1	0.37	2005
Analytic Transient Solution Of Scfl Logic Gates	1	0.39	2005
Robust three-state PFD architecture with enhanced frequency acquisition capabilities	1	0.54	2004
Current output stage with improved CMRR	0	0.34	2003
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers	0	0.34	2000