Name
Title | ||
|---|---|---|
Is it time to include High-Level Synthesis design in Digital System Education for Undergraduate Computer Engineers? |
Abstract | ||
|---|---|---|
We ask the question, "should High-level Synthesis (HLS) design be part of an undergraduate computer engineering education while learning digital system design?". Current trends in industry include an increasing demand for engineers who can build FPGA systems. FPGAs, just like other chips, continue to improve in terms of complexity, speed, available resources, and new features. The design complexity for using an FPGA continues to grow and Hardware Description Languages (HDLs), though a step up in design efficiency compared to schematic design, is a low-level approach akin to assembly language for programmers, and HDLs limits the productivity of an engineer. HLS tools, such as Legup, Intel HLS, and Xilinx's Vivado attempt to provide designers with a higher-level design abstraction providing a means to describe their computation in high-level languages - such as C. As these tools become more mainstream in industry, when should education follow? In this work, we explore how HLS tools might be used by an undergraduate by looking at exemplar designs, a simple RISC-V processor and a basic C loop, and implementing the design in both HDL and HLS. We then analyze the FPGA cost of each implementation. Next, we provide a philosophical discussion based on this experience on what the pros and cons of moving students to HLS design abstraction level are. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401774 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
DocType | ISSN | Citations |
Conference | 0271-4302 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Isaac Nelson | 1 | 0 | 0.34 |
| Ricardo Ferreira | 2 | 49 | 13.81 |
| Jose Augusto Nacif | 3 | 0 | 0.34 |
| Peter Jamieson | 4 | 16 | 7.77 |