Name
Abstract | ||
|---|---|---|
The use of through silicon vias (TSVs) is essential for vertically connecting the individual circuit layers of a 3-D IC. However, because the pitch between TSVs is being decreased, it becomes more vulnerable to bridge defects between the TSVs. In the previous architectures, the parallel topology between the power supply and the bridge defects reduces the resolution of the test results and makes th... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TVLSI.2021.3063651 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Through-silicon vias,Bridge circuits,Integrated circuits,Resistance,Voltage measurement,Stacking,Circuit faults | Journal | 29 |
Issue | ISSN | Citations |
6 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jungil Mok | 1 | 0 | 0.34 |
| Hyeonchan Lim | 2 | 2 | 2.45 |
| Sungho Kang | 3 | 436 | 78.44 |