Title
A High-Throughput Detection Circuit based on 2 q +1-Valued Deep Neural Networks
Abstract
The demands of applications using a high-speed deep learning models at data centers are rapidly increasing. However, most of these accelerators depend on many memory accesses and DSP blocks, which cause performance bottleneck. We present a lookup table (LUT) mapping to directly map convolutional layers, mainly used in modern deep learning models. To reduce the number of LUTs, we develop a training...
Year
DOI
Venue
2021
10.1109/ISMVL51352.2021.00032
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)
Keywords
DocType
ISSN
Training,Deep learning,Data centers,Technological innovation,Solid modeling,Convolution,Tools
Conference
0195-623X
ISBN
Citations 
PageRank 
978-1-7281-9224-6
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Naoto Soga100.34
Ryosuke Kuramochi202.70
Hiroki Nakahara315537.34