Name
Abstract | ||
|---|---|---|
Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of multiple runs of a te... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ETS50041.2021.9465464 | 2021 IEEE European Test Symposium (ETS) |
Keywords | DocType | ISSN |
Fault diagnosis,Resistance,Ports (computers),Torque,Systematics,Random access memory,Built-in self-test | Conference | 1530-1877 |
ISBN | Citations | PageRank |
978-1-6654-1849-2 | 0 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bartosz Grzelak | 1 | 0 | 0.34 |
| Martin Keim | 2 | 0 | 0.34 |
| Artur Pogiel | 3 | 22 | 4.38 |
| Janusz Rajski | 4 | 2460 | 201.28 |
| Jerzy Tyszer | 5 | 838 | 74.98 |