Name
Title | ||
|---|---|---|
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns |
Abstract | ||
|---|---|---|
Two inventions improve DRAM’s core circuits within a 1Gb DDR3 product: (1) Scale VCC down to 0.7V but generate a Restore ONE signal 1.3V into memory cells to enhance Retention-Time at least to 138ms at 125°C. This facilitates scaling VDD and peripheral devices. (2) When addresses are ready in the DRAM-controller, an Interface Circuitry enables pre-decoding Row/Column addresses into the DRAM before other Commands, thus accelerating Random-Access Row/Column Times by 1.5ns, respectively. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492418 | 2021 Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
Retention time,DRAM,inventions | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-6654-4766-9 | 0 | 0.34 |
References | Authors | |
0 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nicky Lu | 1 | 0 | 0.34 |
| Chun Shiah | 2 | 1 | 1.71 |
| Juang-Ying Chueh | 3 | 0 | 0.34 |
| Bor-Doou Rong | 4 | 1 | 1.37 |
| Wei-Jr Huang | 5 | 0 | 0.34 |
| Ho-Yin Chen | 6 | 0 | 0.34 |
| Cheng-Nan Chang | 7 | 0 | 0.34 |
| Chia-Wei Chang | 8 | 0 | 0.34 |
| Tzung-Shen Chen | 9 | 0 | 0.34 |