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BOR-DOOU RONG
Author Info
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Name
Affiliation
Papers
BOR-DOOU RONG
Etron Technology, Hsinchu, Taiwan
4
Collaborators
Citations
PageRank
41
1
1.37
Referers
Referees
References
8
57
4
Publications (4 rows)
Collaborators (41 rows)
Referers (8 rows)
Referees (57 rows)
Title
Citations
PageRank
Year
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns
0
0.34
2021
Session 25 Overview - DRAM Memory Subcommittee.
0
0.34
2021
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems
0
0.34
2019
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
1
0.36
2015
1