Name
Abstract | ||
|---|---|---|
We present a time-interleaved (TI) SAR ADC with 8 channels realizing 8-bit conversion at 1 GS/s each. SNDR is 45 dB at low frequency with an ERBW of 5 GHz limited by sampler distortion. Conventional SAR conversion at high speed with minimum degradation is achieved by leveraging techniques such as early quantization, minimum delay logic, DAC redundancy and gain and offset compensation via the DAC. At 8 GS/s the ADC consumes 26 mW resulting in an efficiency of 30 fJ/conv.-step. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.23919/VLSICircuits52068.2021.9492512 | 2021 Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
TI SAR ADC,SNDR,ERBW,time-interleaved successive-approximation-register analog-to-digital converter,conventional SAR conversion,quantization,minimum delay logic,DAC redundancy,offset compensation,size 16.0 nm,noise figure 45.0 dB,frequency 5.0 GHz,power 26.0 mW,word length 8 bit | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-6654-4766-9 | 0 | 0.34 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ewout Martens | 1 | 75 | 17.77 |
| Davide Dermit | 2 | 8 | 3.91 |
| Mithlesh Shrivas | 3 | 1 | 0.70 |
| Shun Nagata | 4 | 0 | 0.34 |
| Jan Craninckx | 5 | 6 | 2.86 |