Name
Abstract | ||
|---|---|---|
For the first time, we demonstrate an optimization technique to synthesize circuits in the Negative Capacitance FET (NCFET) technology. NCFET is a rapidly emerging technology to replace the currently employed CMOS technology due to its profound ability to overcome the fundamental limit in scaling along with its full compatibility with the existing fabrication process. This is achieved by replacing... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCSI.2021.3103860 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Iron,Solid modeling,Capacitance,Logic gates,Standards,FinFETs,Semiconductor device modeling | Journal | 68 |
Issue | ISSN | Citations |
10 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sami Salamin | 1 | 5 | 2.90 |
| Georgios Zervakis | 2 | 49 | 8.33 |
| Y. S. Chauhan | 3 | 16 | 6.46 |
| J. Henkel | 4 | 4471 | 366.50 |
| Hussam Amrouch | 5 | 251 | 50.22 |