Name
Abstract | ||
|---|---|---|
With the technology evolution, the decrease of transistors size and, thus, the increase of density of transistors per area, System-on-a-chip (SoC) development is becoming more and more complex. If design, verification, and test are considered, it is noticed how challenging it is getting for designers to plan and manage chips with dozens of billions of transistors, where optimization is a keyword t... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/VLSI-SoC53125.2021.9607005 | 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | DocType | ISBN |
Full Custom,Optimization,Cell Generation,EDA,Microelectronics | Conference | 978-1-6654-2614-5 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vitor Hugo F. Maciel | 1 | 0 | 0.34 |
| Germano Girondi | 2 | 0 | 0.34 |
| Elias Ramos | 3 | 0 | 0.34 |
| Ricardo A. L. Reis | 4 | 217 | 48.75 |