Paper Info
Title
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System
Abstract
AbstractDespite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.
Year
DOI
Venue
2021
10.1145/3468145
ACM Transactions on Architecture and Code Optimization
Keywords
DocType
Volume
Integrated voltage regulators, power delivery systems, processor power efficiency, voltage noise, fast dynamic voltage and frequency scaling, CPU, GPU
Journal
18
Issue
ISSN
Citations 
4
1544-3566
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
An Zou172.12
Huifeng Zhu212.37
Jingwen Leng34912.97
Xin He48028.00
Vijay Janapa Reddi52931140.26
Christopher D. Gill678955.35
Xuan Zhang700.68