Name
Abstract | ||
|---|---|---|
Secure silicon requires a seamless integration of new tools, new IP, and design flows to help designers protect integrated circuits from increasingly sophisticated attacks. Independent Validation and Verification (IV&V) of this integrated technology is important to ensure that the tools actually deliver on their security claims when used by independent parties (i.e., people who were not involved in designing the tools). This work discusses the principles and approaches for IV&V of such a complex design environment, including validation of the security strength of the various hardware security techniques, such as combinational and sequential logic locking, Trojan Detection, side-channel mitigation, and blockchain-based asset management. The main challenge in running an IV&V effort is to ensure that the process provides rigorous, methodical and provable evaluation of the claims of not only the component tools and IP, but whether such an integrated environment can produce security-hardened designs by a non-security expert. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/DAC18074.2021.9586302 | 2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC) |
Keywords | DocType | ISSN |
Security-aware electronic design automation, hardware security, validation, verification, blockchain, cryptography | Conference | 0738-100X |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
13 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Benjamin Tan | 1 | 5 | 3.58 |
| Siddharth Garg | 2 | 675 | 55.14 |
| Ramesh Karri | 3 | 0 | 0.34 |
| Yun-Tao Liu | 4 | 29 | 7.42 |
| Michael Zuzak | 5 | 16 | 2.37 |
| Abhisek Chakraborty | 6 | 0 | 0.34 |
| Ankur Srivastava | 7 | 902 | 79.64 |
| Omid Aramoon | 8 | 1 | 3.05 |
| Qian Xu | 9 | 3 | 2.43 |
| Gang Qu | 10 | 0 | 0.34 |
| Adam Porter | 11 | 0 | 0.34 |
| Jeno Szep | 12 | 0 | 0.34 |
| Warren Savage | 13 | 0 | 0.34 |