Name
Title | ||
|---|---|---|
End-to-End Formal Verification of a RISC-V Processor Extended with Capability Pointers |
Abstract | ||
|---|---|---|
Capability Hardware Enhanced RISC Instructions (CHERI) extend conventional ISAs with capabilities that can enable fine-grained memory protection and scalable software compartmentalisation. CHERI-RISC-V is an extended version of the RISC-V ISA with support for CHERI, and Flute is an open-source 64-bit RISC-V processor with a five-stage, in-order pipeline. This case study presents the formal verific... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.34727/2021/isbn.978-3-85448-046-4_10 | 2021 Formal Methods in Computer Aided Design (FMCAD) |
Keywords | DocType | ISBN |
Reduced instruction set computing,Microarchitecture,Design automation,Pipelines,Computer bugs,Hardware,Open source software | Conference | 978-3-85448-046-4 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dapeng Gao | 1 | 72 | 4.00 |
| Thomas F. Melham | 2 | 384 | 35.63 |