Name
Title | ||
|---|---|---|
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter |
Abstract | ||
|---|---|---|
Digital PLLs (DPLLs) have demonstrated to be a promising candidate to implement frequency synthesizers in wireless transceivers, thanks to their scaling-friendly architecture and to the possibility of implementing powerful background adaptive calibration algorithms to compensate the system non-idealities. The combination of these features leads to an inherently faster time-to-market than tradition... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/A-SSCC53895.2021.9634706 | 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | DocType | ISBN |
Phase noise,Wireless communication,Temperature dependence,Jitter,Transceivers,Production facilities,Calibration | Conference | 978-1-6654-4350-0 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mario Mercandelli | 1 | 15 | 4.32 |
| Luca Bertulessi | 2 | 0 | 0.34 |
| Carlo Samori | 3 | 2 | 1.04 |
| Salvatore Levantino | 4 | 0 | 0.68 |