Name
Title | ||
|---|---|---|
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation |
Abstract | ||
|---|---|---|
The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/JSSC.2021.3114205 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Clocks,Random access memory,Transmitters,Receivers,Graphics,Bandwidth,Multiplexing | Journal | 57 |
Issue | ISSN | Citations |
1 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 0 | 24 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ji-Hyo Kang | 1 | 0 | 0.34 |
| Jaehyeok Yang | 2 | 0 | 0.34 |
| Kyunghoon Kim | 3 | 0 | 0.68 |
| Joo-Hyung Chae | 4 | 0 | 0.34 |
| Gang-Sik Lee | 5 | 0 | 0.68 |
| Sangyeon Byeon | 6 | 0 | 0.34 |
| Boram Kim | 7 | 0 | 0.34 |
| Dong-Hyun Kim | 8 | 0 | 0.34 |
| Youngtaek Kim | 9 | 0 | 0.34 |
| Yeongmuk Cho | 10 | 0 | 0.34 |
| Junghwan Ji | 11 | 0 | 0.34 |
| Sera Jeong | 12 | 0 | 0.34 |
| Jaehoon Cha | 13 | 0 | 0.34 |
| Minsoo Park | 14 | 0 | 0.34 |
| Hongdeuk Kim | 15 | 0 | 0.34 |
| Sijun Park | 16 | 0 | 0.34 |
| Sunho Kim | 17 | 0 | 0.68 |
| Hae-Kang Jung | 18 | 0 | 0.34 |
| Jieun Jang | 19 | 2 | 1.41 |
| Sangkwon Lee | 20 | 10 | 2.82 |
| Hyungsoo Kim | 21 | 0 | 0.34 |
| Joo-Hwan Cho | 22 | 0 | 0.68 |
| Junhyun Chun | 23 | 2 | 2.42 |
| Seonyong Cha | 24 | 0 | 0.34 |