Paper Info
Title
A 2.5–32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE
Abstract
This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the PCIe requires wide-range operation and compensation for high insertion loss. The proposed multi-rate CDR engine enables the receiver to operate with multi-rate clocking schemes according to the data rates, which does not need any additional high-speed analog circuits normally used for wide-range operation. In addition, the hybrid DFE architecture not only meets the DFE feedback timing constraint and but also reduces the equalization power. By using clock gating, the receiver can save power when operating at lower generations such as Gen 1, 2, 3, and 4. The prototype chip is fabricated in a 40-nm CMOS technology and occupies an active area of 0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The receiver achieves BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> with various PCIe channels, satisfying PCIe jitter tolerance masks. It consumes 62.7 mW at 32 Gb/s, compensating for 27.5-dB inserting loss, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.07 pJ/b/dB is achieved.
Year
DOI
Venue
2022
10.1109/TCSII.2022.3153396
IEEE Transactions on Circuits and Systems II: Express Briefs
Keywords
DocType
Volume
Hybrid multi-rate DFE,multi-rate clocking,multi-rate CDR,PCIe,wide-range receiver
Journal
69
Issue
ISSN
Citations 
6
1549-7747
0
PageRank 
References 
Authors
0.34
7
9
Name
Order
Citations
PageRank
MC Choi100.34
Sungyoung Lee22932279.41
S Roh300.34
Kwyro Lee426570.73
J Oh500.34
Sekwon Kim631.57
Nam K. Kim7495.85
Wonshik Choi811.03
Young-jin Kim901.69