Name
Title | ||
|---|---|---|
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy |
Abstract | ||
|---|---|---|
It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation stra... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/VLSI-DAT54769.2022.9768095 | 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | DocType | ISBN |
Performance evaluation,Runtime,Heuristic algorithms,Loading,Random access memory,Life estimation,Very large scale integration | Conference | 978-1-6654-0921-6 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kang-Yi Fan | 1 | 0 | 0.34 |
| Jyun-Hua Chen | 2 | 0 | 0.34 |
| Chien-Nan Liu | 3 | 0 | 0.34 |
| Juinn-Dar Huang | 4 | 270 | 27.42 |