Paper Info
Title
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation
Abstract
Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> logic density, 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> energy efficiency, and 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.
Year
DOI
Venue
2022
10.1109/JSSC.2021.3117260
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Atom switch (AS),cross-point,field programmable gate array (FPGA),nonvolatile (NV),programmable logic,resistive random access memory (RRAM),via-switch (VS)
Journal
57
Issue
ISSN
Citations 
7
0018-9200
0
PageRank 
References 
Authors
0.34
22
11
Name
Order
Citations
PageRank
Xu Bai100.34
Naoki Banno200.34
Makoto Miyamura300.34
Ryusuke Nebashi400.34
Koichiro Okamoto500.34
Hideaki Numata600.34
Noriyuki Iguchi700.34
Masanori Hashimoto846279.39
Tadahiko Sugibayashi900.34
Toshitsugu Sakamoto1000.68
Munehiro Tada112412.04