Title
Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic
Abstract
This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.2\times - 17.3\times $ </tex-math></inline-formula> , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.
Year
DOI
Venue
2022
10.1109/TCSI.2022.3151920
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
DocType
Volume
Digital,logic,memristor,multilevel,RRAM,ternary
Journal
69
Issue
ISSN
Citations 
6
1549-8328
0
PageRank 
References 
Authors
0.34
23
9