Name
Abstract | ||
|---|---|---|
This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when ... |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/JSSC.2021.3111924 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Interpolation,Voltage,Latches,Quantization (signal),Switches,Capacitors,Time-domain analysis | Journal | 57 |
Issue | ISSN | Citations |
5 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaegeun Song | 1 | 4 | 2.47 |
| Yunsoo Park | 2 | 7 | 2.52 |
| Chaegang Lim | 3 | 11 | 2.26 |
| Yohan Choi | 4 | 3 | 2.14 |
| Soonsung Ahn | 5 | 0 | 0.34 |
| Sooho Park | 6 | 0 | 0.34 |
| Chulwoo Kim | 7 | 9 | 4.86 |