Author Info
Name
Affiliation
Papers
CHULWOO KIM
Korea Univ, Seoul, South Korea
13
Collaborators
Citations 
PageRank 
57
9
4.86
Referers 
Referees 
References 
50
123
11
Search Limit
100123
Title
Citations
PageRank
Year
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations10.352022
An Output-Boosted 3-ratio Switched-Capacitor DC-DC Converter with 0.5-to-1.8 V Output Voltage Range for Low-Power IoT Applications00.342022
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique00.342022
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End10.362022
A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection00.342022
Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance00.342022
A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode10.402021
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector using Bangbang Duty-Cyle-Detector00.342021
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique00.342021
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.00.342017
F6: Energy-efficient I/O design for next-generation systems00.342014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector30.452014
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface30.602013