Paper Info
Title
Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking
Abstract
DRAM systems continue to be plagued by the Row-Hammer (RH) security vulnerability. The threshold number of row activations ( T RH ) required to induce RH has reduced rapidly from 139K in 2014 to 4.8K in 2020, and T RH is expected to reduce further, making RH even more severe for future DRAM. Therefore, solutions for mitigating RH should be effective not only at current T RH but also at future T RH . In this paper, we investigate the mitigation of RH at ultra-low thresholds (500 and below). At such thresholds, state-of-the-art solutions, which rely on SRAM or CAM for tracking row activations, incur impractical storage overheads (340KB or more per rank at T RH of 500), making such solutions unappealing for commercial adoption. Alternative solutions, which store per-row metadata in the addressable DRAM space, incur significant slowdown (25% on average) due to extra memory accesses, even in the presence of metadata caches. Our goal is to develop scalable RH mitigation while incurring low SRAM and performance overheads. To that end, this paper proposes Hydra, a <u>H</u>ybri<u>d</u> T<u>ra</u>cker for RH mitigation, which combines the best of both SRAM and DRAM to enable low-cost mitigation of RH at ultra-low thresholds. Hydra consists of two structures. First, an SRAM-based structure that tracks aggregated counts at the granularity of a group of rows, and is sufficient for the vast majority of rows that receive only a few activations. Second, a per-row tracker stored in the DRAM-array, which can track an arbitrary number of rows, however, to limit performance overheads, this tracker is used only for the small number of rows that exceed the tracking capability of the SRAM-based structure. We provide a security analysis of Hydra to show that Hydra can reliably issue a mitigation within the specified threshold. Our evaluations show that Hydra enables robust mitigation of RH, while incurring an SRAM overhead of only 28 KB per-rank and an average slowdown of only 0.7% (at T RH of 500).
Year
DOI
Venue
2022
10.1145/3470496.3527421
ISCA: International Symposium on Computer Architecture
Keywords
DocType
ISSN
Memory system, DRAM, Reliability, Security, Row-Hammer
Conference
1063-6897
Citations 
PageRank 
References 
2
0.36
8
Authors
4
Name
Order
Citations
PageRank
Moinuddin K. Qureshi12639110.61
Aditya Rohan220.36
Gururaj Saileshwar320.36
Prashant J. Nair434615.74