Paper Info
Title
Efficient Backside Power Delivery for High-Performance Computing Systems
Abstract
In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {W}/{\mathrm {mm}}^{2}$ </tex-math></inline-formula> power-density target for high-performance computing (HPC) systems, a 25-high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor (300 MHz), 150- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m} V_{\mathrm {DD}}$ </tex-math></inline-formula> -bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -horizontal-pitch nano- through-silicon via ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\eta \,\,=83$ </tex-math></inline-formula> % can be obtained for 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {W}/{\mathrm {mm}}^{2}$ </tex-math></inline-formula> power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.
Year
DOI
Venue
2022
10.1109/TVLSI.2022.3183904
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
DocType
Volume
Air-core inductor,backside power delivery network (PDN),buck converter,system integration,system optimization
Journal
30
Issue
ISSN
Citations 
11
1063-8210
0
PageRank 
References 
Authors
0.34
4
7
Name
Order
Citations
PageRank
Hesheng Lin100.34
G. Van der Plas232835.68
Xiao Sun310.75
Dimitrios Velenis411613.77
Francky Catthoor53932423.30
R. Lauwereins62336220.18
Eric Beyne79625.91