Paper Info
Title
MT-3000: a heterogeneous multi-zone processor for HPC
Abstract
With high performance computing (HPC) continues evolving, high performance microprocessor, which is the key building block of super computer, becomes the jewel in the crown of HPC. To this end, we propose MT-3000, a heterogeneous multi-zone processor for HPC, which is entirely designed and implemented by National University of Defense Technology. MT-3000 contains 16 general purpose CPUs, 96 control cores and 1536 accelerator cores, which are grouped into a general purpose zone and an acceleration zone. The acceleration zone is further divided into four clusters. Through sophisticated designs of such multi-zone organization, interconnection, and memory subsystem, MT-3000 achieves 11.6 TFLOPS double precision performance and 45.4 Gflops/w power efficiency when operating at 1.2 GHz. Based on the MT-3000 chip, a super computer prototype with nearly 12 peta flops peak performance is implemented, achieving 80% computation efficiency for Linpack. The possibility of a larger scale super computer construction based on MT-3000 chip is also elaborated in this paper.
Year
DOI
Venue
2022
10.1007/s42514-022-00095-y
CCF Transactions on High Performance Computing
Keywords
DocType
Volume
HPC, Linpack, Multicore, Computation efficiency
Journal
4
Issue
ISSN
Citations 
2
2524-4922
0
PageRank 
References 
Authors
0.34
2
13
Name
Order
Citations
PageRank
Kai Lu146557.59
Yaohua Wang24414.23
Yang Guo36732.72
Huang Chun400.34
Liu Sheng500.34
Wang Ruibo600.34
Fang Jianbin700.34
Tang Tao800.68
Chen Zhaoyun900.34
Liu Biwei1000.34
Liu Zhong1100.34
Lei Yuanwu1200.34
Sun Haiyan1300.34