Name
Title | ||
|---|---|---|
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption |
Abstract | ||
|---|---|---|
Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]–[3], in-situ error detection and correction (EDAC) [4]–[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6σ local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/CICC53496.2022.9772803 | 2022 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISSN |
mining core,ultra-low-voltage digital circuits,mining expenses,energy cost,energy-efficient bitcoin mining cores,clock frequency adaption,timing slack inference,bitcoin mining core,variation-resilient 64-stage,error correction process,timing errors,local process variation,bulky error detectors,deep pipeline,deeply-pipelined architecture,pessimistic margin,dynamic timing enhancement,EDAC,in-situ error detection,tunable replica circuits,multiphase latch pipeline,energy savings,temperature variations,worst-case process,timing margin,energy-efficiency,voltage 0.3 V | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-7281-8280-3 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jieyu Li | 1 | 0 | 0.34 |
| Weifeng He | 2 | 61 | 14.69 |
| Bo Zhang | 3 | 4 | 19.80 |
| Guanghui He | 4 | 1 | 1.38 |
| Jun Yang | 5 | 147 | 36.54 |
| Mingoo Seok | 6 | 601 | 80.71 |