Name
Abstract | ||
|---|---|---|
Demand for increased data-rates in serial link transceivers calls for innovative architectures capable of overcoming communications impairments such as limited channel bandwidth and stringent jitter specifications. While mixed-signal and ADC-based receiver architectures that utilize simple pulse amplitude modulation (PAM) can take advantage of technology scaling, it is becoming increasingly difficult to deal with the extremely short baseband pulse widths. This paper presents a wireline receiver front-end (RXFE) architecture that supports multicarrier signaling to provide a ~3X relaxation in clock jitter requirements. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/CICC53496.2022.9772868 | 2022 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISSN |
ADC-based receiver architectures,simple pulse amplitude modulation,technology scaling,extremely short baseband pulse widths,wireline receiver front-end architecture,multicarrier signaling,clock jitter requirements,FinFET,data-rates,serial link transceivers,innovative architectures,communication impairments,channel bandwidth,stringent jitter specifications,jitter-robust ADC-based multicarrier receiver front end,mixed-signal based receiver architectures,PAM,RXFE architecture,size 22.0 nm,bit rate 40 Gbit/s | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-7281-8280-3 | 0 | 0.34 |
References | Authors | |
3 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuanming Zhu | 1 | 0 | 0.34 |
| Julian Camilo Gomez Diaz | 2 | 0 | 0.34 |
| Srujan Kumar Kaile | 3 | 0 | 0.68 |
| II-Min Yi | 4 | 0 | 0.68 |
| Tong Liu | 5 | 0 | 0.68 |
| Sebastian Hoyos | 6 | 234 | 29.24 |
| Samuel Palermo | 7 | 0 | 1.01 |