Name
Title | ||
|---|---|---|
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler |
Abstract | ||
|---|---|---|
Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-core oscillators [2], [3] or multi-core PLLs [4] have been explored to trade power consumption against phase noise, the theoretical phase-noise reduction of 3dB per each doubling of the number of cores is never fully obtained in practice. The second issue of the QN introduced at the DCO analog/digital domain crossing could be in principle solved by increasing DCO resolution, but this comes at the cost of a larger number of DCO bits which entails higher design complexity and larger area occupation. Alternatively, a
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modulator driving the DCO can be used to high-pass-shape the QN and its clock oversampled with respect to the reference frequency to move the QN bump in the spectrum to higher frequency. Prior solutions to generate the
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clock are based either on an auxiliary PLL which multiplies the reference clock frequency or a high-speed frequency divider that divides the DCO output [3]. While in the first case pulling phenomena between auxiliary and main PLL are observed to worsen performance, in the second case, the frequency divider may consume large power and metastability in the crossing between the two non-synchronous clock domains has to be addressed. This work presents a 9GHz fractional-N digital bang-bang PLL (BBPLL) achieving 72fs rms total integrated jitter (including spurs) at near-integer channels and -140.7dBc/Hz spot phase-noise level at 10MHz offset. The PLL relies on a low-power quadrupler calibrated by a background digital-period-averaging (DPA) algorithm to reduce the QN of the
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DCO, and on a low-noise true-in-phase combiner (TIPC) which combines two PLL cores to reduce phase noise. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/CICC53496.2022.9772796 | 2022 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISSN |
ΔΣ modulator,reference frequency,QN bump,auxiliary PLL,reference clock frequency,high-speed frequency divider,nonsynchronous clock domains,total integrated jitter,low-power quadrupler,background digital-period-averaging algorithm,true-in-phase combiner,PLL cores,phase noise,calibrated frequency quadrupler,fractional-N PLLs,modern wireless standards,spot-noise,digitally controlled oscillator,quantization noise,frequency granularity,multicore oscillators,multicore PLLs,theoretical phase-noise reduction,DCO resolution,DCO bits,design complexity,total-lntegrated-jitter fractional-N digital PLL,fractional-N digital bang-bang PLL,frequency 9.0 GHz,time 72.0 fs,time 100.0 fs,noise figure 3.0 dB,frequency 10.0 MHz | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-7281-8280-3 | 1 | 0.35 |
References | Authors | |
0 | 13 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Francesco Buccoleri | 1 | 3 | 1.74 |
| Simone M. Dartizio | 2 | 2 | 1.04 |
| Francesco Tesolin | 3 | 2 | 1.42 |
| Luca Avallone | 4 | 1 | 0.35 |
| Alessio Santiccioli | 5 | 4 | 1.06 |
| Agata Iesurum | 6 | 1 | 0.35 |
| Giovanni Steffan | 7 | 1 | 0.35 |
| Andrea Bevilacqua | 8 | 236 | 38.57 |
| Luca Bertulessi | 9 | 15 | 4.73 |
| Dmytro Cherniak | 10 | 1 | 0.35 |
| Carlo Samori | 11 | 349 | 39.76 |
| Andrea L. Lacaita | 12 | 320 | 42.41 |
| Salvatore Levantino | 13 | 351 | 43.23 |