Name
Abstract | ||
|---|---|---|
In the recent years, machine learning techniques have successfully been applied in various fields of digital circuit development including logic synthesis. One of the approaches is evolutionary resynthesis. It is based on the idea of iterative local optimization of parts of the original circuit. The main advantage is the possibility to mitigate various scalability issues connected with the usage of evolutionary algorithms. However, success of this method depends heavily on the ability to identify suitable candidates for local optimization. Despite that, it has been shown that the local optimization produces significantly compact solutions compared to the evolutionary optimization performed at the level of the original circuit. In this paper, we analyze how the local optimization affects the delay of the circuit and propose a modified approach to the optimization of digital circuits. Compared to the existing techniques, the proposed method allows the presence of the non-uniform delay at the inputs of the circuits selected for the local optimization. This modification enables to maintain the delay of the optimized circuit at a reasonable level without a significant overhead. The evaluation done on a set of non-trivial highly optimized benchmark circuits representing various real-world circuits demonstrated that our method is able to remove a significant number of gates while preserving the delay at the original value. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/ISVLSI54635.2022.00045 | 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | DocType | ISSN |
Logic optimization,Cartesian Genetic Programming,Evolutionary Resynthesis | Conference | 2159-3469 |
ISBN | Citations | PageRank |
978-1-6654-6606-6 | 0 | 0.34 |
References | Authors | |
12 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jitka Kocnová | 1 | 0 | 0.34 |
| Zdenek Vasicek | 2 | 0 | 0.68 |