Name
Title | ||
|---|---|---|
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications |
Abstract | ||
|---|---|---|
Three-dimensional integration offers architectural and performance benefits for scaling augmented/virtual reality (AR/VR) models on highly resource-constrained edge devices. Two-dimensional off-chip memory interfaces are too prohibitively energy intensive and bandwidth (BW) limited for AR/VR devices. To solve this, we propose using advanced 3-D stacking technology for high-density vertical integration to local memory and compute, increasing memory capacity within the same footprint at iso-BW with improvements in energy and latency. We evaluate 3-D architectures for a prototype AR/VR accelerator to demonstrate up to 3.9× latency reduction and 1.6× lower energy compared to a 2-D configuration within a smaller/similar footprint. Additionally, we show the feasibility of deploying higher resolution AR/VR models by stacking multiple tiers of memory, providing a pathway to break the footprint constraints of 2-D architectures. The use of high-density 3-D interconnects allows us to demonstrate localized benefits at the accelerator-level compared with standard system-on-chip memory disaggregation techniques/architectures. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/MM.2022.3202254 | IEEE Micro |
DocType | Volume | Issue |
Journal | 42 | 6 |
ISSN | Citations | PageRank |
0272-1732 | 0 | 0.34 |
References | Authors | |
4 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lita Yang | 1 | 0 | 0.34 |
| Robert M. Radway | 2 | 0 | 0.34 |
| Yu-Hsin Chen | 3 | 0 | 0.34 |
| Tony F. Wu | 4 | 0 | 0.34 |
| Huichu Liu | 5 | 0 | 0.34 |
| Elnaz Ansari | 6 | 0 | 0.34 |
| Vikas Chandra | 7 | 691 | 59.76 |
| Subhasish Mitra | 8 | 3657 | 228.90 |
| Edith Beigne | 9 | 536 | 52.54 |