Fazal Hameed - Citegraph

Author Info

Name	Affiliation	Papers
FAZAL HAMEED	Karlsruhe Institute of Technology (KIT), Germany	17
Collaborators	Citations	PageRank
29	54	7.25
Referers	Referees	References
119	309	130

Search Limit

100309

Publications (17 rows)

Collaborators (29 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling	0	0.34	2021
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory	0	0.34	2021
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0	5	0.45	2020
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade	6	0.50	2020
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories	1	0.36	2020
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory	0	0.34	2019
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.	0	0.34	2019
RTSim: A Cycle-accurate Simulator for Racetrack Memories	7	0.52	2019
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.	4	0.45	2018
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.	1	0.35	2018
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization.	1	0.35	2017
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.	1	0.37	2016
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.	0	0.34	2016
Reducing latency in an SRAM/DRAM cache hierarchy via a novel Tag-Cache architecture	9	0.76	2014
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache	4	0.40	2013
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores	10	0.61	2013
Dynamic cache management in multi-core architectures through run-time adaptation	5	0.46	2012

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