Name
Title | ||
|---|---|---|
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. |
Abstract | ||
|---|---|---|
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM due to its low leakage and scalability advantages. In fact, although being more energy-efficient than SRAM, STT-MRAM caches at higher levels (e.g. L3) still incur a high energy consumption due to 1) high leakage in their read and write circuits and 2) high dynamic write energy in their bit-cells. To address this problem, we propose a novel normally-off STT-MRAM cache that exploits the fact that most applications access zero-byte patterns very frequently. In this architecture, writing of zero-bytes is avoided to reduce write energy. In addition, all read and write circuits are by default power gated (i.e. normally-off) to reduce leakage power. Then, dynamically at runtime, only those circuits required for the ongoing operation are activated. Our evaluations for an L3-cache of a multi-core microprocessor show that this approach reduces the energy consumption by 60% compared to state-of-the-art, while its impact on performance is negligible. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2934583.2934629 | ISLPED |
Keywords | Field | DocType |
MRAM, Cache, Zero-Byte, Compression, Normally-Off | Leakage (electronics),Efficient energy use,Computer science,Cache,Static random-access memory,Magnetoresistive random-access memory,Real-time computing,Computer hardware,Energy consumption,Random access,Scalability | Conference |
Citations | PageRank | References |
0 | 0.34 | 24 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fabian Oboril | 1 | 288 | 26.71 |
| Fazal Hameed | 2 | 54 | 7.25 |
| Rajendra Bishnoi | 3 | 132 | 19.64 |
| Ali Ahari | 4 | 16 | 2.43 |
| helia naeimi | 5 | 338 | 23.24 |
| Mehdi B. Tahoori | 6 | 1537 | 163.44 |