Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| A 45nm Soi Compiled Embedded Dram With Random Cycle Times Down To 1.3ns | 2 | 0.44 | 2010 |
| Advancements in at-speed array BIST: multiple improvements. | 3 | 0.47 | 2007 |
| Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering | 7 | 0.98 | 2002 |