Name
Abstract | ||
|---|---|---|
This paper discusses the unique challenges in constructing an architecture and methodology for testing a 1GHz 65nm Embedded DRAM in an ASIC environment. The concepts of multiplication of both test commands and test clock frequency are discussed in detail. The novel technique of command multiplication is thoroughly explored The inherent benefits of this design point is examined as it relates to test circuit design, BIST sharing, and chip level wiring in comparison to traditional scan or parallel based array BIST architectures. Attention is also paid to various methods used for supporting at-speed/high-speed test clock generation from a low speed tester and the important influence this has on test cost and test quality. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TEST.2007.4437566 | ITC |
Keywords | Field | DocType |
DRAM chips,application specific integrated circuits,built-in self test,ASIC environment,at-speed array BIST,at-speed high-speed test clock generation,chip level wiring,command multiplication,embedded DRAM,frequency 1 GHz,size 65 nm,test circuit design | Dram,Computer science,Test quality,Circuit design,Application-specific integrated circuit,Electronic engineering,Chip,Multiplication,Computer hardware,Clock rate,Embedded system,Built-in self-test | Conference |
ISSN | Citations | PageRank |
1089-3539 | 3 | 0.47 |
References | Authors | |
14 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kevin Gorman | 1 | 3 | 0.47 |
| Michael Roberge | 2 | 5 | 1.59 |
| Adrian Paparelli | 3 | 5 | 0.91 |
| Gary Pomichter | 4 | 12 | 1.90 |
| Stephen Sliva | 5 | 5 | 0.91 |
| William Corbin | 6 | 7 | 0.88 |