Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. | 0 | 0.34 | 2016 |
| Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs | 0 | 0.34 | 2013 |
| Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM | 1 | 0.36 | 2013 |