Name
Title | ||
|---|---|---|
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs |
Abstract | ||
|---|---|---|
This paper proposes a cost-effective TAP-controlled serialized compressed scan architecture (SCSA) design to support known-good-die (KGD) test, known-good-stack (KGS) test and post-bond test in the 3D stacked ICs (3D-SICs) configuration. Additionally, a serialized compressed signal generator (SCSG) design is also developed of the proposed scheme to generate the corresponding controlled signals for SCSA to ensure the test cost reduction. Experimental results and comparisons show that the proposed scheme can effectively achieve the good performance in test pin count and test time reduction with little extra hardware overhead penalty. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ATS.2013.29 | Asian Test Symposium |
Keywords | Field | DocType |
integrated circuit testing,scsg,compressed scan architecture,stacked ics,tap-controlled serialized compressed scan architecture,3d stacked ic,three-dimensional integrated circuits,known-good-die test,corresponding controlled signal,scsa,test time reduction,post-bond test,signal generator,proposed scheme,good performance,cost-effective,test cost reduction,3d-sic,design for testability,costing,test pin count,extra hardware overhead penalty | Design for testing,Architecture,Computer science,Signal generator,Electronic engineering,Test compression,Activity-based costing,Cost reduction,Embedded system | Conference |
ISSN | Citations | PageRank |
1081-7735 | 0 | 0.34 |
References | Authors | |
1 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen-An Chen | 1 | 1 | 1.04 |
| Yee-Wen Chen | 2 | 2 | 1.39 |
| Chun-Lung Hsu | 3 | 59 | 14.53 |
| Ming-Hsueh Wu | 4 | 1 | 1.04 |
| Kun-Lun Luo | 5 | 24 | 2.83 |
| Bing-chuan Bai | 6 | 1 | 1.72 |
| Liang-Chia Cheng | 7 | 37 | 6.46 |