GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs | 4 | 0.41 | 2008 |
Automatic generation of complex properties for hardware designs | 24 | 1.43 | 2008 |
An Integrated SystemC Debugging Environment | 7 | 0.88 | 2007 |
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs | 5 | 0.60 | 2007 |
A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator | 0 | 0.34 | 2007 |
A high-level target-precise model for designing reconfigurable HW tasks | 1 | 0.39 | 2006 |
Non-Intrusive High-level SystemC Debugging | 1 | 0.44 | 2006 |
IPQ: IP Qualification for Efficient System Design | 2 | 0.48 | 2004 |
Use of HDL Code Checkers to Support the IP Entrance Check " A Requirement Analysis | 0 | 0.34 | 2002 |
Enhanced Reusability for SoC-Based HW/SW Co-Design | 5 | 0.72 | 2002 |
Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. | 1 | 0.39 | 2002 |
Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. | 0 | 0.34 | 1998 |
Low Power Design Of Fsms By State Assignment And Disabling Self-Loops | 2 | 0.64 | 1997 |