Name
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IPDPS.2007.370390 | IPDPS |
Keywords | Field | DocType |
data flow graphs,field programmable gate arrays,high level synthesis,optimisation,reconfigurable architectures,resource allocation,control flow graph,data flow graph,field programmable gate arrays,hardware tasks,high-level synthesis,optimization,register-transfer-level,resource sharing,run-time reconfigurable FPGA architecture | Computer architecture,Control flow graph,Computer science,High-level synthesis,Parallel computing,Data-flow analysis,Field-programmable gate array,Resource allocation,Register-transfer level,Shared resource,Reference design | Conference |
Citations | PageRank | References |
5 | 0.60 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maik Boden | 1 | 19 | 3.33 |
| Thomas Fiebig | 2 | 9 | 1.01 |
| Torsten Meibner | 3 | 5 | 0.60 |
| Steffen Rülke | 4 | 52 | 7.40 |
| Jürgen Becker | 5 | 1894 | 259.42 |