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IL-MIN YI
Author Info
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Name
Affiliation
Papers
IL-MIN YI
Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea
8
Collaborators
Citations
PageRank
22
21
3.66
Referers
Referees
References
61
194
41
Search Limit
100
194
Publications (8 rows)
Collaborators (22 rows)
Referers (61 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
1
0.39
2018
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
0
0.34
2017
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
3
0.44
2016
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
1
0.39
2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
4
0.60
2016
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination
2
0.40
2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface
6
0.56
2014
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.
4
0.53
2012
1