A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths | 0 | 0.34 | 2013 |
Multispeculative additive trees in high-level synthesis | 3 | 0.40 | 2013 |
Multispeculative Addition Applied to Datapath Synthesis. | 11 | 0.70 | 2012 |
Power optimization in heterogenous datapaths. | 0 | 0.34 | 2011 |
Software metadata: Systematic characterization of the memory behaviour of dynamic applications | 9 | 0.68 | 2010 |
Using speculative functional units in high level synthesis | 5 | 0.47 | 2010 |
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption | 0 | 0.34 | 2009 |
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption | 0 | 0.34 | 2009 |
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information | 5 | 0.47 | 2008 |
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis | 2 | 0.38 | 2008 |
HW-SW emulation framework for temperature-aware design in MPSoCs | 23 | 1.22 | 2007 |
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip | 14 | 0.82 | 2007 |
Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption | 3 | 0.42 | 2007 |
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems | 9 | 0.92 | 2006 |
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip | 35 | 2.27 | 2006 |
Pre-synthesis optimization of multiplications to improve circuit performance | 4 | 0.44 | 2006 |
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems | 15 | 0.78 | 2006 |
Systematic dynamic memory management design methodology for reduced memory footprint | 22 | 1.04 | 2006 |
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications | 7 | 0.62 | 2005 |
Reducing memory fragmentation with performance-optimized dynamic memory allocators in network applications | 2 | 0.43 | 2005 |
Behavioural Scheduling to Balance the Bit-Level Computational Effort | 0 | 0.34 | 2004 |
Memory-access-aware data structure transformations for embedded software with dynamic data accesses | 21 | 1.11 | 2004 |
An integrated hardware/software approach for run-time scratchpad management | 81 | 3.61 | 2004 |
Source Code Transformation to Improve Conditional Hardware Reuse | 0 | 0.34 | 2002 |
High-level synthesis of multiple-precision circuitsindependent of data-objects length. | 0 | 0.34 | 2002 |
A Unified Algorithm for Mutual Exclusiveness Identification | 2 | 0.45 | 1999 |