Paper Info
Title
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis
Abstract
A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, resource allocation and binding of behavioral specifications. It overcomes the limitations of low-power algorithms and based on a bit-level timing model and a study of the target technology, tries to chain in the same cycle as many operations as possible. It also fragments the functional units, not the operations, for diminishing the required hardware. We also keep a minimum performance by estimating the cycle time while we are chaining operations. This way we obtain a reduction for both the static power and the dynamic one. We achieve an additional dynamic power reduction by studying the Hamming distance and applying partial or total commutative property. Experimental results on real circuits show great improvements in both power and energy consumption and performance over conventional low power algorithms.
Year
DOI
Venue
2008
10.1109/DSD.2008.120
DSD
Keywords
Field
DocType
behavioral specification,power aware high level,static power,bit-level timing model,hamming distance,energy consumption,conventional low power algorithm,minimum performance,restricted chaining,cycle time,additional dynamic power reduction,complete power-aware high-level synthesis,fragmentation techniques,schedules,allocation,resource management,adders,high level synthesis,scheduling,commutative property,resource allocation,formal specification,registers,low power electronics,functional unit,scheduling algorithm
Chaining,Commutative property,Computer science,High-level synthesis,Parallel computing,Real-time computing,Schedule,Dynamic demand,Resource allocation,Hamming distance,Energy consumption
Conference
Citations 
PageRank 
References 
2
0.38
11
Authors
5
Name
Order
Citations
PageRank
Alberto A. Del Barrio17814.49
María C. Molina2101.25
José M. Mendías327319.60
Esther Andres420.38
Roman Hermida51048.19