Title
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Abstract
State of the art multi-objective synthesis flows use to degrade some parameters of the circuit while trying to optimize the target one. This paper addresses the power reduction problem in heterogeneous datapaths, while keeping a similar area and execution time with respect to the baseline case. Our specific approach first diminishes the area via fragmentation techniques and afterwards it gives it back with the introduction of Low Power Functional Units (LP-FUs) that occupy more area than their corresponding non-low power counterparts. Furthermore, a fragmentation algorithm more suitable for power reduction is proposed. Results show that it is possible to diminish power by 27% on average (49% in the best case).
Year
DOI
Venue
2013
10.1016/j.vlsi.2012.02.005
Integration
Keywords
Field
DocType
art multi-objective synthesis flow,low power functional units,baseline case,low power heterogenous datapaths,power reduction,fragmentation algorithm,best case,similar area,fragmentation technique,corresponding non-low power counterpart,power reduction problem,aware high-level synthesis flow,area,high level synthesis
Computer science,High-level synthesis,Flow (psychology),Parallel computing,Fragmentation (computing),Real-time computing,Execution time
Journal
Volume
Issue
ISSN
46
2
0167-9260
Citations 
PageRank 
References 
0
0.34
20
Authors
5
Name
Order
Citations
PageRank
Alberto A. Del Barrio17814.49
Seda Öǧrenci Memik248842.57
María C. Molina3776.97
José M. Mendías427319.60
Román Hermida58915.34