Name
Title | ||
|---|---|---|
0.3-1.5v Embedded Sram Core With Write-Replica Circuit Using Asymmetrical Memory Cell And Source-Level-Adjusted Direct-Sense-Amplifier |
Abstract | ||
|---|---|---|
This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V-dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V-dd above 0.5 V than those of using the control with logic-gate-delay. However, as V-dd is reduced below 0.5 V and gets close to the threshold voltage (V-th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I-d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I-d) and V-th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I-d and V-th is the prerequisite for the SRAM control in the range of Vdd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I-d and V-th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V-dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietele/e88-c.4.630 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
SRAM, low-voltage, wide-voltage, SoC | Sense amplifier,Logic gate,Static random-access memory,Electronic engineering,Low voltage,Engineering,Electrical engineering,Integrated circuit,Threshold voltage,Amplifier,Memory cell | Journal |
Volume | Issue | ISSN |
E88C | 4 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshi-kazu Suzuki | 1 | 73 | 11.00 |
| Yoshinobu Yamagami | 2 | 67 | 10.80 |
| Ichiro Hatanaka | 3 | 0 | 0.34 |
| Akinori Shibayama | 4 | 0 | 0.34 |
| Hironori Akamatsu | 5 | 67 | 11.37 |
| Hiroyuki Yamauchi | 6 | 180 | 30.79 |