GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs | 4 | 0.41 | 2008 |
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs | 5 | 0.60 | 2007 |
A high-level target-precise model for designing reconfigurable HW tasks | 1 | 0.39 | 2006 |
A Low-Cost Realization of an Adaptable Protocol Processing Unit | 2 | 0.43 | 2005 |
Cost-Efficient Implementation of Adaptive Finite State Machines | 1 | 0.39 | 2004 |
Enhanced Reusability for SoC-Based HW/SW Co-Design | 5 | 0.72 | 2002 |
Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. | 1 | 0.39 | 2002 |