Name
Playground
About
FAQ
GitHub
Playground
Shortest Path Finder
Community Detector
Connected Papers
Author Trending
Michael Kerrigan
Zaheer Ul Haq
Claudia Calabrese
Hao Mao
Peter Malec
Giovanni Venturelli
Chen Ma
J-L Risler
Radu Timofte
Kuanrui Yin
Home
/
Author
/
JULIAN VIEJO
Author Info
Open Visualization
Name
Affiliation
Papers
JULIAN VIEJO
Grupo ID2 (Investigacion y Desarrollo Digital) ETSI Informatica (Tec. Electronica), Universidad de Sevilla, Sevilla, Spain 41012
6
Collaborators
Citations
PageRank
9
1
2.17
Referers
Referees
References
3
34
13
Publications (6 rows)
Collaborators (9 rows)
Referers (3 rows)
Referees (34 rows)
Title
Citations
PageRank
Year
Studying The Viability Of Static Complementary Metal-Oxide-Semiconductor Gates With A Large Number Of Inputs When Using Separate Transistor Wells
0
0.34
2011
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
0
0.34
2011
Comprehensive Analysis On The Internal Power Dissipation Of Static Cmos Cells In Ultra-Deep Sub-Micron Technologies
0
0.34
2010
Design and implementation of a suitable core for on-chip long-term verification
0
0.34
2010
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
0
0.34
2008
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements
1
0.48
2006
1