Name
Title | ||
|---|---|---|
Studying The Viability Of Static Complementary Metal-Oxide-Semiconductor Gates With A Large Number Of Inputs When Using Separate Transistor Wells |
Abstract | ||
|---|---|---|
The so-called body effect as well as internal parasitic capacitances impose strong performance limitations on complementary metal-oxide-semiconductor (CMOS) static logic gates such as decreased speed, increased power consumption and high variation of the pin-to-pin delay along the inputs. The severity of this problem increases with the number of inputs of the gate. Like silicon-on-insulator (SOI) technologies, triple-well technologies make it possible to circumvent the body effect by using independent body terminals for each transistor in a series tree, thus allowing the practical implementation of gates with a larger number of inputs. In this paper the authors study the viability of gates with large number of inputs using both, the traditional and the proposed design styles in a regular bulk-CMOS technology. Electrical simulation results on a set of test gates show remarkable performance improvements in delay and power consumption of independent body gates at the expense of a significant area penalty. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1166/jolpe.2011.1145 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | DocType | Volume |
Low Power, High Speed, CMOS Digital Gates, Body Effect, Parasitic Capacitance | Journal | 7 |
Issue | ISSN | Citations |
3 | 1546-1998 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Guerrero | 1 | 14 | 5.86 |
| Alejandro Millán | 2 | 10 | 5.77 |
| Jorge Juan | 3 | 7 | 3.46 |
| Manuel J. Bellido | 4 | 82 | 11.82 |
| Paulino Ruiz-de-clavijo | 5 | 21 | 6.72 |
| Enrique Ostúa | 6 | 3 | 3.05 |
| Julian Viejo | 7 | 1 | 2.17 |