Paper Info
Title
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification
Abstract
Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product. Test cases play an important role in determining the quality of a design. Inadequate test-cases may cause bugs to remain after verification. Although TLM expedites the verification of a hardware design, the problem of having high coverage test cases remains unsettled at this level of abstraction. In this paper, first, in order to generate test-cases for a TL model we present a Control-Transaction Graph (CTG) describing the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and Transactions represent the interactions such as synchronization between the modules. Second, we define dependent paths (DePaths) on the CTG as test-cases for a transaction level model. The generated DePaths can find some communication errors in simulation and detect unreachable statements concerning interactions. We also give coverage metrics for a TL model to measure the quality of the generated test-cases. Finally, we apply our method on the SystemC model of AMBA-AHB bus as a case study and generate testcases based on the CTG of this model.
Year
DOI
Venue
2007
10.1109/DSD.2007.63
DSD
Keywords
Field
DocType
integrated circuit design,functional testing,automatic test pattern generation,system on chip,control flow graph,synchronisation,formal verification
Automatic test pattern generation,System on a chip,Control flow graph,Computer science,Transaction-level modeling,SystemC,Real-time computing,Integrated circuit design,Test case,Formal verification
Conference
ISBN
Citations 
PageRank 
0-7695-2978-X
1
0.38
References 
Authors
7
3
Name
Order
Citations
PageRank
Mohammad Reza Kakoee1878.68
M. H. Neishaburi2797.51
Siamak Mohammadi36210.62