| ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces | 1 | 0.40 | 2015 |
| A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report. | 0 | 0.34 | 2013 |
| EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment | 8 | 0.80 | 2013 |
| Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis | 0 | 0.34 | 1997 |
| A Graph Based Processor Model for Retargetable Code Generation | 15 | 1.48 | 1996 |
| Software Synthesis for real-time information processing systems | 6 | 0.58 | 1995 |
| Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures | 0 | 0.34 | 1995 |
| Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures | 13 | 6.95 | 1995 |
| Code Generation for Embedded Processors [Dagstuhl Workshop, August 31 - September 2, 1994] | 14 | 13.07 | 1995 |
| Bit-alignment for retargetable code generators. | 4 | 1.46 | 1994 |
| Optimal scheduling and software pipelining of repetitive signal flow graphs with delay line optimization | 2 | 0.51 | 1994 |
| Data routing: a paradigm for efficient data-path synthesis and code generation. | 30 | 5.60 | 1994 |
| Instruction set definition and instruction selection for ASIPs | 72 | 7.69 | 1994 |
| Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures | 2 | 1.36 | 1994 |
| Design of heterogeneous ICs for mobile and personal communication systems | 9 | 2.54 | 1994 |
| CHESS: Retargetable Code Generation For Embedded DSP Processors | 59 | 9.26 | 1994 |
| Scheduling with register constraints for DSP architectures | 3 | 0.50 | 1994 |
| A generalized state assignment theory for transformations on signal transition graphs | 44 | 7.46 | 1994 |
| Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers | 2 | 0.66 | 1992 |
| Clustering techniques for register optimization during scheduling preprocessing | 9 | 1.92 | 1991 |
| An integrated automatic design system for complex DSP algorithms | 0 | 0.34 | 1990 |
