Name
Affiliation
Papers
YI-PING YOU
National Chiao Tung University, Hsinchu, Taiwan
21
Collaborators
Citations 
PageRank 
35
143
12.89
Referers 
Referees 
References 
191
480
315
Search Limit
100480
Title
Citations
PageRank
Year
Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform00.342019
CLPKM: A checkpoint-based preemptive multitasking framework for OpenCL kernels.20.382019
A static region-based compiler for the Dalvik virtual machine00.342016
VecRA: A Vector-Aware Register Allocator for GPU Shader Processors.00.342016
Vector-aware register allocation for GPU shader processors10.362015
Enabling OpenCL support for GPGPU in Kernel-based Virtual Machine50.492014
Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs40.392014
Energy-aware code motion for GPU shader processors30.422013
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files120.692009
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores30.412008
Compilation for compact power-gating controls120.582007
Enabling compiler flow for embedded VLIW DSP processors with distributed register files70.542007
Palf: Compiler Supports For Irregular Register Files In Clustered Vliw Dsp Processors60.482007
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains30.382007
Compilers for leakage power reduction371.292006
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors50.602006
Low-power techniques for network security processors00.342005
A sink-n-hoist framework for leakage power reduction90.772005
Compiler supports and optimizations for PAC VLIW DSP processors122.232005
Power-Aware scheduling for parallel security processors with analytical models20.382004
Compiler analysis and supports for leakage power reduction on microprocessors201.172002