Paper Info
Title
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
Abstract
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.
Year
DOI
Venue
2007
10.1145/1273444.1254793
Sigplan Notices
Keywords
Field
DocType
embedded vliw dsp compilers,distributed regis- ter files,software pipelining
Programming language,Software pipelining,Instruction scheduling,Very long instruction word,Computer science,Parallel computing,Register file,Compiler,Real-time computing,Optimizing compiler,Texas Instruments DaVinci,Data flow diagram
Conference
Volume
Issue
ISSN
42
7
0362-1340
Citations 
PageRank 
References 
7
0.54
6
Authors
7
Name
Order
Citations
PageRank
Chung-Kai Chen1778.28
Ling-Hua Tseng270.54
Shih-Chang Chen315213.78
Young-Jia Lin470.54
Yi-Ping You514312.89
Chia-Han Lu6222.32
Jenq Kuen Lee745948.71