Author Info
Name
Affiliation
Papers
DAVID VILLEGER
Ecole Superieure d'Ingenieurs d'Electrotechnique et d'Electronique 2 Boulevard Blaise Pascal BP 99 93162 Noisy le Grand Cedex France
3
Collaborators
Citations 
PageRank 
3
194
31.07
Referers 
Referees 
References 
433
33
28
Search Limit
100433
Title
Citations
PageRank
Year
A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach13116.481996
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology5411.701995
An integrated multiplier for complex numbers92.891994